1.1.1 Structure and function of the processor
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1
Three main things which affect a CPU's SPEED:
- Cache size
- Clock speed
- Number of cores
- Clock speed
- Number of cores
2
Control Unit?
Coordinates all actions in the CPU and directs the flow of data by sending control signals and decodes instructions.
3
Program Counter (PC)?
Holds address of next instruction to be executed.
4
Memory address register (MAR)?
-Holds address of the memory location from which data/instructions are to be fetched from
-Copies address from PC
-Copies address from PC
5
Memory data register (MDR)?
-Temporarily stores data from memory.
-All data from and to memory must go through this.
-All data from and to memory must go through this.
6
Current instruction register
Holds current instruction being executed which is split into opcode + operand
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Arithmetic logic unit (ALU)
Performs arithmetic and logic operations on data
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Accumulator?
Holds calculation results from ALU
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What is a bus?
Wires that transport data between components
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Three buses we need to know?
- Address bus
- Data bus
- Control bus
- Data bus
- Control bus
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Address bus?
-Transports memory address that identifies where data needs to be read from or written to
-Unidirection from processor to memory
-Unidirection from processor to memory
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Data bus?
- Transports instructions/data between components
- Bidirection
- Bidirection
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Control bus
-Carries control signals between internal and external components
-Bidirection
-Bidirection
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Fetch steps?
1) PC is checked as it holds address of next instruction to be executed.
2) MAR copies address in PC
3) Address is sent through address bus to main memory and waits for signal from control bus
4) CU sends read signal through control bus to main memory
5) Data from memory is sent through data bus to MDR
6) Data is copied to CIR (as we are currently fetching an instruction)
7) PC is incremented (we have now fetched instruction)
2) MAR copies address in PC
3) Address is sent through address bus to main memory and waits for signal from control bus
4) CU sends read signal through control bus to main memory
5) Data from memory is sent through data bus to MDR
6) Data is copied to CIR (as we are currently fetching an instruction)
7) PC is incremented (we have now fetched instruction)
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Decode steps?
CU decodes instruction (lets say opcode says to LDA memory location 0101 into accumulator.)
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Execute steps?
1) Send memory address (0101) to MAR
2) Address is sent through address bus to main memory
3) CU sends a read signal through control bus to main memory
4) Contents stored in memory address 0101 is sent through data bus to MDR
5) Contents in MDR is copied to accumulator
2) Address is sent through address bus to main memory
3) CU sends a read signal through control bus to main memory
4) Contents stored in memory address 0101 is sent through data bus to MDR
5) Contents in MDR is copied to accumulator
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Whats pipelining?
The process of doing the Fetch,Decode,Execute cycles of 3 instructions simultaneously, preventing registers being idle.
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Types of pipelining?
-Instruction
-Arithmetic
-Arithmetic
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Instruction pipelining?
separating out the instruction into fetching, decoding, and executing.
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Arithmetic pipelining?
Breaking down arithmetic operations and overlapping them as they are performed
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What is flushing in pipelining?
Whenever instructions are being FDE but due to a branch they aren't needed and so are removed. Can slow down processor.
22
Von neumann architecture?
- Memory space is shared between instructions and data
- Instructions/data stored in same format(RW etc)
- Single CU follows linear FDE cycle
- One system bus
- Instructions/data stored in same format(RW etc)
- Single CU follows linear FDE cycle
- One system bus
23
Harvard architecture?
- Instructions and data are stored in two different memory spaces
- Instructions and data can be in different formats
- Reading/writing data can be done at same time as fetching instructions(parallel processing)
- Two system buses
- Instructions and data can be in different formats
- Reading/writing data can be done at same time as fetching instructions(parallel processing)
- Two system buses
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Contemporary processing?
Modern processing combining both harvard and von neumann processing