1.1.1 Structure and function of the processor

- Cache size
- Clock speed
- Number of cores

Coordinates all actions in the CPU and directs the flow of data by sending control signals and decodes instructions.

Holds address of next instruction to be executed.

-Holds address of the memory location from which data/instructions are to be fetched from
-Copies address from PC

-Temporarily stores data from memory.
-All data from and to memory must go through this.

Holds current instruction being executed which is split into opcode + operand

Performs arithmetic and logic operations on data

Holds calculation results from ALU

Wires that transport data between components

- Address bus
- Data bus
- Control bus

-Transports memory address that identifies where data needs to be read from or written to
-Unidirection from processor to memory

- Transports instructions/data between components
- Bidirection

-Carries control signals between internal and external components
-Bidirection

1) PC is checked as it holds address of next instruction to be executed.
2) MAR copies address in PC
3) Address is sent through address bus to main memory and waits for signal from control bus
4) CU sends read signal through control bus to main memory
5) Data from memory is sent through data bus to MDR
6) Data is copied to CIR (as we are currently fetching an instruction)
7) PC is incremented (we have now fetched instruction)

CU decodes instruction (lets say opcode says to LDA memory location 0101 into accumulator.)

1) Send memory address (0101) to MAR
2) Address is sent through address bus to main memory
3) CU sends a read signal through control bus to main memory
4) Contents stored in memory address 0101 is sent through data bus to MDR
5) Contents in MDR is copied to accumulator

The process of doing the Fetch,Decode,Execute cycles of 3 instructions simultaneously, preventing registers being idle.

-Instruction
-Arithmetic

separating out the instruction into fetching, decoding, and executing.

Breaking down arithmetic operations and overlapping them as they are performed

Whenever instructions are being FDE but due to a branch they aren't needed and so are removed. Can slow down processor.

- Memory space is shared between instructions and data
- Instructions/data stored in same format(RW etc)
- Single CU follows linear FDE cycle
- One system bus

- Instructions and data are stored in two different memory spaces
- Instructions and data can be in different formats
- Reading/writing data can be done at same time as fetching instructions(parallel processing)
- Two system buses

Modern processing combining both harvard and von neumann processing