Computer Architecture Exam 1

Computer Technology is changing at a ___ pace.

Architectural attributes include ___.

Computer ___ refers to those attributes that have a direct impact on the logical execution of a program.

It is a(n) ___ issue whether a computer will have a multiply instruction.

It is a(n) ___ issue whether the multiply instruction will be implemented by a special multiply unit or by a mechanism that makes repeated use of the add unit of the system.

A ___ system is a set of interrelated subsystems.

An I/O device is referred to as a ___.

When data is moved over longer distances, to or from a remote device, the process is known as ___.

The ___ stores data.

The ___ moves data between the computer and its external environment.

A common example of system interconnection is by means of a ___.

A ___ is a mechanism that provides for communication among CPU, main memory, and I/O.

___ provides storage internal to the CPU.

The ___ performs the computer's data processing functions.

___ refers to those attributes of a system visible to a programmer.

___ refers to the operational units and their interconnections that realize the architectural specifications.

Control Signals, Interfaces between the computer, and Peripherals, and the memory technology used are all examples of ___ attributes.

The Instruction Set, the number of bits used to represent various data types, I/O mechanisms, and techniques for addressing memory are all examples of ___ attributes.

The ___ architecture is the architecture of IBM's mainframe product line.

___ is the way in which components are interrelated.

___ is the operation of each individual component as part of the structure.

The basic functions that a computer can perform are: Data Processing, Data Movement, Control, and ____.

When data is received from, or delivered to a device that is directly connected to the computer, the process is known as ___.

The four main structural components of the computer are: Main Memory, I/O, System Interconnection, and ___.

Often referred to as the processor, the ___ controls the operations of the computer and performs its data processing functions.

A common example of system interconnection is by means of a ___, consisting of a number of conducting wires to which all the other components attach.

The major structural components of the CPU are: Control Unit, Register, CPU Interconnection, and ___.

A ___ Control Unit operates by executing micro-instructions that define the functionality of the Control Unit.

The ___ controls the operations of the CPU and hence the computer.

Multiple parallel pipelines are used in ___.

The desktop applications(s) that require great power of today's microprocessor-based system include ___.

___ potentially increases the amount of work available for the processor to execute.

The interface between the processor and ___ is the most crucial pathway in the entire computer because it is responsible for carrying a constant flow of program instructions and data between memory chips and the processor.

The ___ is a relatively small fast memory interposed between a larger, slower memory and the logic that accesses the larger memory.

An increase in clock rate means that individual operations are executed ___.

A ___ is a core designed to perform parallel operations on graphics data.

A(n) ___ Mean is a good candidate for comparing the execution time performance of several systems.

___ law deals with the potential speedup of a program using multiple processors compared to a single processor.

One increment, or pulse of a clock is referred to as a ___.

The use of multiple processors on the same chip is referred to as ___ and provides the potential to increase performance without increasing the clock rate.

With respect to changes in values, the ___ Mean gives equal weight to all of the values in the data set.

The ___ measures the ability of a computer to complete a single task.

A measurement of how many tasks a computer can accomplish in a certain amount of time is called a(n) ___.

The best known of the SPEC benchmark suites is ___.

__________ enables a processor to work simultaneously on multiple instructions by performing a different phase for each of the multiple instructions at the same time.

___________ is the ability to issue more than one instruction in every processor clock cycle.

With __________ the processor looks ahead in the instruction code fetched from memory and predicts which branches, or groups of instructions, are likely to be processed next.

__________ enables the processor to keep its execution engines as busy as possible by executing instructions that are likely to be needed.

Traditionally found on a plug-in graphics card, a _________ is used to encode and render 2D and 3D graphics as well as process video.

__________ Law applies to a queuing system.

The three common formulas used for calculating a mean or Arithmetic, Harmonic, and ___.

The __________ Mean used for a time-based variable, such as program execution time, has the important property that it is directly proportional to the total time.

The _________ Mean is preferred when calculating rates.

The __________ Mean gives consistent results regardless of which system is used as a reference.

_________ metric are required for all reported results and have strict guidelines for compilation.

A _________ suite is a collection of programs, defined in a high-level language, that together attempt to provide a representative test of a computer in a particular application or system programming area.

At the most fundamental level, the speed of a processor is dictated by the pulse frequency produced by the clock, measured in cycles per second, or _________.

The best-known collection of benchmark suites is defined and maintained by an industry consortium known as __________.

__________ law deals with the potential speedup of a program using multiple processors compared to a single processor.

Virtually all contemporary computer designs are based on concepts developed by __________ at the Institute for Advanced Studies, Princeton.

The von Neumann architecture is based on which concept?

A sequence of codes or instructions is called __________.

The processing required for a single instruction is called a(n) ___ cycle.

A(n) ___ is generated by a failure such as power failure or memory parity error.

A(n) _________ is generated by some condition that occurs as a result of an instruction execution.

The interconnection structure must support which transfer?

A bus that connects major computer components (processor, memory, I/O) is called a ___.

The __________ are used to designate the source or destination of the data on the data bus.

The data lines provide a path for moving data among system modules and are collectively called the _________.

A __________ is the high-level set of rules for exchanging packets of data between devices.

Each data path consists of a pair of wires (referred to as a __________ ) that
transmits data one bit at a time.

The _________ receives read and write requests from the software above the TL and creates request packets for transmission to a destination via the link layer.

The TL supports which of the following address spaces?

The QPI _________ layer is used to determine the course that a packet will traverse across the available system interconnects.

A __________ register specifies the address in memory for the next read or write.

A _________ register contains the data to be written into memory or receives the data read from memory.

The most common classes of interrupts are: program, timer, I/O and ________.

A(n) _________ interrupt is generated by a timer within the processor and allows the operating system to perform certain functions on a regular basis.

A(n) ________ interrupt is generated by an I/O controller to signal normal completion of an operation, request service from the processor, or to signal a variety of error conditions.

A _________ interrupt simply means that the processor can and will ignore that interrupt request signal.

The collection of paths connecting the various modules is called the _________ structure.

A __________ is a communication pathway connecting two or more devices

The _________ lines are used to control the access to and the use of the data and address lines.

The purpose of the PCIe __________ layer is to ensure reliable delivery of packets across the PCIe link.

With _________ transmission signals are transmitted as a current that travels down one conductor and returns on the other.

The QPI link layer performs two key functions: flow control and _________ control.

The __________ is a popular high-bandwidth, processor-independent bus that can function as a mezzanine or peripheral bus.

The _________ function is needed to ensure that a sending QPI entity does not overwhelm a receiving QPI entity by sending data faster than the receiver can process the data and clear buffers for more incoming data.

__________ refers to whether memory is internal or external to the computer.

Internal memory capacity is typically expressed in terms of _________.

For internal memory, the __________ is equal to the number of electrical lines into and out of the memory module.

“Memory is organized into records and access must be made in a specific linear sequence” is a description of __________.

Individual blocks or records have a unique address based on physical location with ___.

For random-access memory, __________ is the time from the instant that an address is presented to the memory to the instant that data have been stored or made available for use.

The ________ consists of the access time plus any additional time required before a second access can commence.

A portion of main memory used as a buffer to hold data temporarily that is to be read out to disk is referred to as a _________.

A line includes a _________ that identifies which particular block is currently being stored.

__________ is the simplest mapping technique and maps each block of main memory into only one possible cache line.

When using the __________ technique all write operations made to main memory are made to the cache as well.

The key advantage of the __________ design is that it eliminates contention for the cache between the instruction fetch/decode unit and the execution unit.

The Pentium 4 ___ component executes micro-operations, fetching the required data from L1 data cache and temporarily storing the result in registers.

In reference to access time to a two-level memory, a _________ occurs if an accessed word is not found in the faster memory.

A logical cache stores data using ___.

__________ memory consists of peripheral storage devices, such as disk and tape.

One byte equals __________ bits.

From a user’s point of view the two most important characteristics of memory are capacity and _____________.

The three performance parameters for memory are: access time, transfer rate, and _________.

_________ is a random access type of memory that enables one to make a comparison of desired bit locations within a word for a specified match, and to do this for all words simultaneously, thus retrieving a word based on a portion of its contents rather than its address.

The ________ rate is the rate at which data can be transferred into or out of a memory unit.

The most commonly used physical types of memory are: semiconductor memory, __________ memory (used for disk and tape), and optical and magneto-optical.

The three key characteristics of memory are capacity, access time, and _______.

External, nonvolatile memory is referred to as ___________ or auxiliary memory.

The cache consists of blocks called __________.

The Pentium 4 processor core consists of four major components: fetch/decode unit, out-of-order execution logic, memory subsystem, and __________.

The __________ units execute micro-operations, fetching the required data from the L1 data cache and temporarily storing results in registers.

__________ memory is a facility that allows programs to address memory from a logical point of view, without regard to the amount of main memory physically available.

For set-associative mapping the cache control logic interprets a memory address as three fields: Set, Word, and __________.