1Why is it useful for addresses to fit in the CPU word size?
Otherwise address calculations need several instructions
2How much memory can a 16-bit address access?
$2^{16}$ = 64 KB
3How much memory can a 32-bit address access?
$2^{32}$ = 4 GB
4How much memory can a 20-bit address access?
1 MB
5How much memory can a 40-bit address access?
1 TB
6How much memory can an 8-bit address access?
256 B
7What is the 8088 segmented effective address formula?
$\text{EA} = \text{Segment} \times 16 + \text{Address}$
8How many address bits did 8088 segmented addressing give?
20 bits (1 MB)
9What was the main limitation of segmented addressing?
Arrays were limited to 64 KB without costly segment register changes
10Why is there no universal microprocessor architecture?
The requirements of high performance, low energy and low cost conflict
11What are the three classes of Flynn's classification?
SISD, SIMD and MIMD
12What is SISD?
Single instruction, single data: the uniprocessor (von Neumann) architecture
13What is SIMD?
Single instruction, multiple data: array/vector processors doing the same instruction on many data
14What is MIMD?
Multiple instruction, multiple data: parallel processors
15Which of these are SIMD instruction sets?
- ARM NEON
- x86 SSE
- x86 AVX
- ARM Thumb
16Which Flynn class does a multicore processor belong to?
17Which Flynn class do GPU-style vector operations belong to?
18What are von Neumann's five computer components?
Input, output, memory, ALU, control unit
19Which components form the CPU?
The ALU and the control unit
20Which components are the peripherals?
Input and output devices
21What is the Princeton architecture?
A single memory space and bus shared by instructions and data
22What is the von Neumann bottleneck?
Instructions and data must be fetched sequentially over one shared bus
23What are the advantages of the Princeton architecture?
Simple for programmers; instructions can be treated as data
24What is a risk of the Princeton architecture?
Data can be accidentally executed as instructions, crashing the CPU
25What is the Harvard architecture?
Separate instruction and data memories with separate buses
26What is the main advantage of the Harvard architecture?
Instructions and data can be fetched simultaneously, doubling memory bandwidth
27How does the Harvard architecture improve security?
Data can't be executed as instructions
28What is the main disadvantage of the Harvard architecture?
Two address spaces, making constants in program memory awkward to read
29Why is the Harvard architecture usually only implemented on-chip?
Multiple external buses are expensive
30Can Harvard instruction and data buses have different widths?
Yes, e.g. a 14-bit instruction bus with an 8-bit data bus
31Why was Harvard awkward in C before 2013?
C had no support for multiple memory spaces, so a pointer was ambiguous
32What is the smallest addressable unit of memory?
A byte
33What is the modified Harvard architecture?
Separate instruction and data buses that share one memory space
34What is the advantage of the modified Harvard architecture?
Harvard speed while looking like Princeton to the programmer
35How does the modified Harvard architecture link its buses?
Bridges built from multiplexers and tri-state buffers
36Why did DSPs use the modified Harvard architecture?
To quickly access constants like FIR coefficients stored with the program
37What algorithm are DSPs designed to compute rapidly?
FIR filtering (multiply-accumulate)
38What is the hybrid architecture?
Separate on-chip instruction and data caches with a single external bus and memory
39How does a hybrid architecture appear internally and externally?
Harvard internally, Princeton externally
40What does the hybrid architecture combine?
Harvard memory bandwidth with Princeton's single address space
41Why use a single external bus in a hybrid architecture?
To reduce pin count and bus wires
42What is the typical layout of a single address space, from address 0 upwards?
Vectors, program code, static data, heap, (free space), stack, peripherals
43In a single address space, what does the heap hold?
Dynamic variables
44In a single address space, what does the data section hold?
Static variables
45Which way do the stack and heap grow?
Towards each other: the heap upwards, the stack downwards
46What is Symmetrical Multiprocessing (SMP)?
A few identical processors sharing a common memory
47What is a core?
A CPU with its own local caches
48Why does each SMP processor have a cache?
To reduce the shared main memory bottleneck
49What problem do per-core caches cause in SMP?
Cache consistency (coherence) problems
50What is Massively Parallel Processing (MPP)?
Many processors with distributed memory communicating over a network
51Which of these are MPP network topologies?
52Where are MPP architectures used?
Supercomputers
53Which is harder to program: SMP or MPP?
MPP
54What is the downside of generic (unified) pointers on a Harvard architecture?
They need an extra byte and are slower, due to a runtime address space check
55What is an instruction set architecture (ISA)?
What an assembly programmer or compiler writer sees of a computer architecture
56What does an ISA include?
Instruction set, data types, addressing modes and register set
57Which of these are typical ISA registers?
- Program counter
- Stack pointer
- Status register
- Cache tag
58What is another name for the program counter?
Instruction pointer (IP)
59Which flags are typically in the status register?
N, V, C, Z (negative, overflow, carry, zero)
60What are the two broad categories of CPU instructions?
Control and data
61What is a control instruction, in operand terms?
A data instruction whose destination is the program counter
62How are ISAs classified by operand count?
Stack (zero), accumulator (one), general purpose register (two or three)
63In a stack ISA, where do operands come from and go?
Sources are popped off the stack; results are pushed on
64What calculator style does a stack ISA resemble?
Reverse Polish notation (RPN)
65What is the advantage of a stack ISA?
Very short instructions, since ALU operands are implicit
66What is the main disadvantage of a stack ISA?
The stack becomes a bottleneck and isn't randomly addressable
67Which two registers would you expect in a stack ISA?
The stack pointer and the program counter
68How do stack architectures usually reduce memory traffic?
By keeping the top two stack locations in registers
69What is the stack ISA code for C = A + B?
PUSH A; PUSH B; ADD; POP C
70What is the instruction count for C = A + B on a stack ISA?
4
71Which processor used a stack ISA for floating point?
The Intel 387 coprocessor
72What is an accumulator ISA?
One explicit operand; the accumulator holds the other operand and every ALU result
73What is the main disadvantage of an accumulator ISA?
The accumulator is the only CPU storage, so memory traffic is high
74Why were accumulator ISAs popular with early microprocessors?
Memory was as fast as the CPU, and instructions were short
75What is the accumulator ISA code for C = A + B?
LOAD A; ADD B; STORE C
76What is the instruction count for C = A + B on an accumulator ISA?
3
77Why do high-performance computers use general purpose register ISAs?
Registers are much faster than memory
78What characterises general purpose register ISAs?
Many registers, all operands explicit, and longer instructions
79How many general purpose registers do register ISAs typically have?
8, 16 or 32
80What two characteristics classify general purpose register ISAs?
Two or three operands per ALU instruction, and how many memory operands (0–3)
81What are the three main register ISA classes?
Memory-memory, register-memory and register-register (load/store)
82What is a memory-memory ISA?
An ALU instruction can have two or more memory operands
83What is the memory-memory code for C = A + B?
ADD A, B, C
84What is the instruction count for C = A + B on a memory-memory ISA?
1
85What is the advantage of a memory-memory ISA?
Fewest instructions and no operand restrictions; easier for assembly programmers
86What is a register-memory ISA?
An ALU instruction can have at most one memory operand
87What is the register-memory code for C = A + B?
LOAD A, R0; ADD B, R0, R1; STORE R1, C
88What is the instruction count for C = A + B on a register-memory ISA?
3
89What is a register-register (load/store) ISA?
ALU instructions can't use memory operands; only loads and stores access memory
90What is the load/store code for C = A + B?
LOAD A, R0; LOAD B, R1; ADD R0, R1, R2; STORE R2, C
91What is the instruction count for C = A + B on a load/store ISA?
4
92Which register ISA has the largest instruction count?
- Register-register (load/store)
- Register-memory
- Memory-memory
93Which register ISA needs the most registers?
Register-register (load/store)
94Which ISA style is associated with CISC?
Memory-memory
95Which ISA style is associated with RISC?
Register-register (load/store)
96Why do modern processors use load/store ISAs despite larger instruction counts?
Simpler instructions are easier to pipeline
97What are the pros and cons of three-operand instructions?
Simpler compiler code generation and scheduling, but more bits to encode
98Why does the AVR use two-operand instructions?
To reduce the bits needed to encode instructions
99Why do modern microcontrollers have many registers?
The CPU–memory speed gap has grown, so registers avoid slow memory accesses
100How have CPU and DRAM performance changed over time?
CPU speed grew much faster than DRAM, widening the gap
101What is register transfer language (RTL)?
A notation for describing CPU operations as register and memory transfers
102In RTL, what does M[R0] mean?
The memory location addressed by R0
103In RTL, what does <- mean?
Assignment
104In RTL, what does ; separate?
Operations that happen in parallel
105In RTL, what does &A mean?
The address of variable A
106What is the RTL for the indirect load LOAD *R1, R0?
R0 <- M[R1]
107What is the RTL for PUSH R0 with 16-bit registers and a descending stack?
M[SP - 2] <- R0; SP <- SP - 2
108What is the RTL for the stack ISA ADD instruction?
M[SP + 4] <- M[SP + 4] + M[SP]; SP <- SP + 4
109What is the RTL for the accumulator instruction ADD B?
ACC <- ACC + M[&B]
110What does IC stand for in ISA comparisons?
Instruction count
111Which language stores operands on a stack?