CompArch Ch. 15 Review

determines the control and pipeline organization.
A. Calculation
B. Execution sequencing
C. Operations performed
D. Operands used

_________ is the fastest available storage device.
A. Main memory
B. Cache
C. Register storage
D. HLL

The first commercial RISC product was _________.
A. SPARC
B. CISC
C. VAX
D. the Pyramid

_________ instructions are used to position quantities in registers temporarily for computational operations.
A. Load-and-store
B. Window
C. Complex
D. Branch

Which stage is required for load and store operations?
A. I
B. E
C. D
D. all of the above

A ________ instruction can be used to account for data and branch delays.
A. SUB
B. NOOP
C. JUMP
D. all of the above

The instruction location immediately following the delayed branch is referred to as the ________.
A. delay load
B. delay file
C. delay slot
D. delay register

A tactic similar to the delayed branch is the _________, which can be used on LOAD instructions.
A. delayed load
B. delayed program
C. delayed slot
D. delayed register

The MIPS R4000 uses ________ bits for all internal and external data paths and for addresses, registers, and the ALU.
A. 16
B. 32
C. 64
D. 128

All MIPS R series processor instructions are encoded in a single ________ word format.
A. 4-bit
B. 8-bit
C. 16-bit
D. 32-bit

A _________ architecture is one that makes use of more, and more fine-grained pipeline stages.
A. parallel
B. superpipelined
C. superscalar
D. hybrid

The R4000 can have as many as _______ instructions in the pipeline at the same time.
A. 8
B. 10
C. 5
D. 3

SPARC refers to an architecture defined by ________.
A. Microsoft
B. Apple
C. Sun Microsystems
D. IBM

The R4000 pipeline stage where the instruction result is written back to the register file is the __________ stage.
A. write back
B. tag check
C. data cache
D. instruction execute