CompArch Ch. 14 Review

__________ are a set of storage locations.
A. Processors
B. PSWs
C. Registers
D. Control units

The ________ controls the movement of data and instructions into and out of the processor.
A. control unit
B. ALU
C. shifter
D. branch

________ registers may be used only to hold data and cannot be employed in the calculation of an operand address.
A. General purpose
B. Data
C. Address
D. Condition code

__________ are bits set by the processor hardware as the result of operations.
A. MIPS
B. Condition codes
C. Stacks
D. PSWs

The _________ contains the address of an instruction to be fetched.
A. instruction register
B. memory address register
C. memory buffer register
D. program counter

The _________ contains a word of data to be written to memory or the word most recently read.
A. MAR
B. PC
C. MBR
D. IR

The ________ determines the opcode and the operand specifiers.
A. decode instruction
B. fetch operands
C. calculate operands
D. execute instruction

_________ is a pipeline hazard.
A. Control
B. Resource
C. Data
D. All of the above

A ________ hazard occurs when there is a conflict in the access of an operand location.
A. resource
B. data
C. structural
D. control

A _________ is a small, very-high-speed memory maintained by the instruction fetch stage of the pipeline and containing the n most recently fetched instructions in sequence.
A. loop buffer
B. delayed branch
C. multiple stream
D. branch prediction

The _________ is a small cache memory associated with the instruction fetch stage of the pipeline.
A. dynamic branch
B. loop table
C. branch history table
D. flag

The _________ stage includes ALU operations, cache access, and register update.
A. decode
B. execute
C. fetch
D. write back

________ is used for debugging.
A. Direction flag
B. Alignment check
C. Trap flag
D. Identification flag

The ARM architecture supports _______ execution modes.
A. 2
B. 8
C. 11
D. 7

The OS usually runs in ________.
A. supervisor mode
B. abort mode
C. undefined mode
D. fast interrupt mode