CompArch Ch. 18 Review

With _______, register banks are replicated so that multiple threads can share the use of pipeline resources.
A. SMT
B. pipelining
C. scalar
D. superscalar

_________ is where individual instructions are executed through a pipeline of stages so that while one instruction is executing in one stage of the pipeline, another instruction is executing in another stage of the pipeline.
A. Superscalar
B. Scalar
C. Pipelining
D. Simultaneous multithreading

_________ is when multiple pipelines are constructed by replicating execution resources, enabling parallel execution of instructions in parallel pipelines so long as hazards are avoided.
A. Vectoring
B. Superscalar
C. Hybrid multithreading
D. Pipelining

One way to control power density is to use more of the chip area for ________.
A. multicore
B. cache memory
C. silicon
D. resistors

Lotus Domino or Siebel CRM are examples of ___________ applications.
A. threaded
B. multi-process
C. Java
D. multi-instance

Oracle database, SAP, and PeopleSoft are examples of ________ applications.
A. Java
B. multithreaded native
C. multi-instance
D. multi-process

_______ applications that can benefit directly from multicore resources include application servers such as Sun's Java Application Server, BEA's Weblogic, IBM's Websphere, and the open-source Tomcat application server.
A. Multi-instance
B. Multi-process
C. Java
D. Threaded

Putting rendering on one processor, AI on another, and physics on another is an example of _________ threading.
A. coarse
B. multi-instance
C. fine-grained
D. hybrid

A loop that iterates over an array of data can be split up into a number of smaller parallel loops in individual threads that can be scheduled in parallel when using ________ threading.
A. multi-process
B. fine-grained
C. hybrid
D. coarse

The _________ is an example of splitting off a separate, shared L3 cache, with dedicated L1 and L2 caches for each core processor.
A. IBM 370
B. ARM11 MPCore
C. AMD Opteron
D. Intel Core i7

The ________ connects to the external bus, known as the Front Side Bus, which connects to main memory, I/O controllers, and other processor chips.
A. L2
B. APIC
C. bus interface
D. all of the above

The Intel Core i7-990X, introduced in 2008, implements ______ x86 SMT processors, each with a dedicated L2 cache, and with a shared L3 cache.
A. 2
B. 4
C. 6
D. 8

Processors are called ________.
A. dies
B. cores
C. QPI
D. interconnects

The ________ feature enables moving dirty data from one CPU to another without writing to L2 and reading the data back in from external memory.
A. migratory lines
B. DDI
C. VFP unit
D. IPIs

The ________ is responsible for maintaining coherency among L1 data caches.
A. VFP unit
B. distributed interrupt controller
C. snoop control unit (SCU)
D. watchdog