Chapter 4: Processor Fundamentals

1. Contents of PC are copied to MAR
2. PC is incrimented by 1
3. MAR fetches data at given address and loads into the MDR
4. Contents of MDR copied to CIR
5. Instructions are decoded by CPU; executed by CIR
6. Cycle repeats.

Temporary storage of data that needs to be or has been processed

- Program Counter (PC)
- Memory Data Register (MDR)
- Memory Address Register (MAR)
- Current Instruction Register (CIR)
- Index Register (IX)
- Accumulator (ACC)
- Status Register (SR)

Stores address of the next instruction to be fetched

Stores data received from Memory.

Stores address where data needs that needs to be fetched is located then sent to MDR.

Stores data received from MDR

Stores a value that is used to calculate an address.

Stores values temporarily after an execution of instruction by the ALU

Contains independant bits/flags; each flag is set based on an event

Carries out arithmetic and logical operations like input and output; part of the processor

Sends & receives signals to control operations like input and output; helps coordinate actions of different components

A memory unit that is directly accessed by the processor

Generates the timing signals that synchronises the components on the motherboard

- Processor type and number of cores
- Cache Memory
- Bus Width
- Clock Speed

Each instruction is executed on a single clock pulse; the faster the clock speed, the more instructions that can be executed per second.

The number of directly addressable memory locations to transfer data between.

Stores frequently / recently used information so that it can be quickly accessed

Connects through USB port (on PC) for input and output devices,
(bi-directional data transfer, meaning can read and write data on USB drive)

Only connects to output devices,
- Unidirectional port
- Allows transmission of video transissions; no audio

Only connects to output devices
- Transmit high-bandwidth&resolution video and audio streams through HDMI ports.

Bidirectional bus that carries data instructions between CPU, memory, and I/O devices

Unidirectional bus that address of main memory location or I/O device aout to be used, from CPU to MAR

- Bidirectional & Unidirectional
- Tranmits control signals from Control Unit (CU) to memory (RAM) or I/O devices to initiate data transfer

A signal from a program seeking processors attention.
- Interrupt Service Routine (ISR)
- Handles interrupts by controlling the processor
- Different ISRs used for different sources of interrupt.

A low-level programming language with instructions made up of Opcodes and Operands

- Immediate
- Direct
- Indirect
- Indexed
- Relative

Operand is the value used in the instruction
(LDM, LDR)

Loads contents from the address into the ACC
(LDD, STO)

The address to be used is at the given address
(LDI, CMI)

Form the address from the given address plus the contents of the Index Register (IX)
(LDX)

The address to be used is an offset number of location away, relative to the address of the current instruction
(No operand)
e.g block of memory starts from address 100, instruction: "LDD 16", Loads contents of address 116 to accumulator.