Chapter 7

-Every instruction executed by the CPU requires memory access (Primary and Secondary)
Primary memory: holds program instructions and data
Secondary storage: is used for long term storage

ALU (arithmetic logic unit)
- Performs calculations and comparisons
CU (control unit)
- Performs fetch/execute cycle
- Runs program instructions and issues commands to the ALU
- Moves data to and from CPU registers and other hardware components
Subcomponents
1. Memory management unit (supervises fetching instructions and data from memory)
2. I/O Interface: sometimes combined with the memory (management unit as the Bus Interface Unit)

a visual representation of a system that uses simple, labeled blocks that represent single or multiple items, entities or concepts, connected by lines to show relationships between them.

pic on cue card

ALU, I/O Interface, CU, program counter, memory
pic on cue card

Small, permanent storage locations within the CPU used for a particular purpose
-Manipulated directly by the Control Unit
-Wired for specific function
-Size in bits or bytes (not in MB like memory)
-Can hold data, an address, or an instruction

1. Use of Registers: (Scratchpad for currently executing program, Holds data needed quickly or frequently, Stores information about status of CPU and currently executing program, Address of next program instruction, Signals from external devices)
2. General Purpose Registers: (User-visible or program-visible registers, Hold intermediate results or data values, e.g., loop counters, Equivalent to LMC’s calculator, Typically several dozen in current CPUs)

1. Program Counter Register (PC) Also called instruction pointer (IP)
2. Instruction Register (IR) Stores instruction fetched from memory
3. Memory Address Register (MAR)
4. Memory Data Register (MDR)
5. Status Registers
- Status of CPU and currently executing program
- Flags (one bit Boolean variable) to track conditions likearithmetic carry and over

1. Stores values from other locations (registers and memory)
2. Addition and subtraction
3. Shift or rotate data
4. Test contents for conditions such as zero or positive

1. Each memory location has a unique address
2. Address from an instruction is copied to the MAR, which finds the location in memory
3. CPU determines if it is a store or retrieval
4. Transfer takes place between the MDR and memory
5. MDR is a two way register

crucial components in the process of reading from and writing to the computer's memory.
slide 12-14

an electronic circuit that stores one bit of binary information
- it must be set to store a logic 1 (high voltage level) and reset to store a logic 0 (low voltage level). Its value is maintained/stored until it is changed by the seteset process.

Determined by two factors
1. Number of bits in the MAR
- LMC = 100 (00 to 99)
- 2^K where K = width of the register in bits
2. Size of the address portion of the instruction
- 4 bits allows 16 locations
- 8 bits allows 256 locations
- 32 bits allows 4,294,967,296 or 4 GB
- 64 bits allows 16 EB (exabytes)

1. DRAM (Dynamic RAM)
Most common, cheap, less electrical power, less heat, smaller space
Volatile: must be refreshed (recharged with power) 1000’s of times each second
2. SRAM (static RAM)
Faster and more expensive than DRAM
Volatile
Small amounts are often used in cache memory for highspeed memory access

ROM Read-only Memory:
- Holds software that is not expected to change over the life of the system such as firmware used for the system BIOS
Flash Memory:
- Inexpensive nonvolatile secondary storage
- Useful for nonvolatile portable computer storage, digital cameras, tablets, smartphones
- Slower rewrite time compared to RAM

Two-cycle process because both instructions and data are in memory
1. Fetch
- Decode or find instruction, load from memory into register and signal ALU
2. Execute
- Performs operation that instruction requires
- Move/transform data

1. PC → MAR Transfer the address from the PC to the MAR
2. MDR → IR Transfer the instruction to the IR
3. IR[address] → MAR Address portion of the instruction loaded in MAR
4. MDR → A Actual data copied into the accumulator
5. PC + 1 → PC Program Counter incremented

1. PC → MAR Transfer the address from the PC to the MAR
2. MDR → IR Transfer the instruction to the IR
3. IR[address] → MAR Address portion of the instruction loaded in MAR
4. A → MDR* Accumulator copies data into MDR
5. PC + 1 → PC Program Counter incremented
*Notice how Step #4 differs for LOAD and STORE

1. PC → MAR Transfer the address from the PC to the MAR
2. MDR → IR Transfer the instruction to the IR
3. IR[address] → MAR Address portion of the instruction loaded in MAR
4. A + MDR → A Contents of MDR added to contents of accumulator
5. PC + 1 → PC Program Counter incremented

SUBTRACT
PC → MAR
MDR → IR
IR[addr] → MAR
A – MDR → A
PC + 1 → PC

BRANCH
PC → MAR
MDR → IR
IR[addr] → PC

BRANCH on Condition
PC → MAR
MDR → IR
If condition true: IR[addr] → PC
If condition false: PC + 1 → PC

HALT
PC → MAR
MDR → IR

INPUT
PC → MAR
MDR → IR
IOR → A
PC + 1 → PC

OUTPUT
PC → MAR
MDR → IR
A → IOR
PC + 1 → PC

Data Movement (load, store)
- Most common, greatest flexibility
- Involve memory and registers
- What’s the size of a word? 16, 32, or 64 bits?
Arithmetic
- Operators + - / * ^
- Integers and floating point
Boolean Logic
- Often includes at least AND, XOR, and NOT
Single operand manipulation instructions
- Negating, decrementing, incrementing, set to 0

1. Bit manipulation instructions
- Flags to test for conditions
2. Shift and rotate
3. Program control
4. Stack instructions
5. Multiple data instructions
6. I/O and machine control

PC:
- Jump and branch
- Subroutine call and return

Stack:
- LIFO method for organizing information
- Items removed in the reverse order from how they are added

Direction given to a computer and causes electrical signals to be sent through specific circuits for processing

Instruction set:
Design defines functions performed by the processor
Differentiates computer architecture by the:
- Number of instructions
- Complexity of operations performed by individual instructions
- Data types supported
- Format (layout, fixed vs. variable length)
- Use of registers
- Addressing (size, modes)

Fixed vs. variable size:
- Pipelining has mostly eliminated variable instruction size architectures
(Most current architectures use 32-bit or 64-bit words)
Addressing Modes:
- Direct
- Mode used by the LMC
- Register Deferred
- Also immediate, indirect, indexed
ex. slide 38