Micro 3-2 Yu
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1
A standard 8-bit Microprocessor Unit (MPU).
Z80
2
What two external components are strictly required for the Z80 to function as a complete system?
An External Oscillator and External Logic Gates.
3
It provides the single-phase system clock frequency to synchronize and drive internal operations.
External Oscillator
4
They generate specific control signals required for the CPU to communicate with Memory and I/O devices.
External Logic Gates
5
What is the architecture and physical package of the Z80?
It is an 8-bit general-purpose microprocessor in a 40-pin Dual-In-Line Package (DIP).
6
What power supply does the Z80 require?
A single +5V DC supply and a Ground (GND) connection.
7
What is the performance frequency range of the Z80?
2.5 MHz to 8 MHz.
8
Which instruction set is the Z80 upward compatible with?
The Intel 8080 instruction set (though it is not pin-compatible).
9
It is a 16-bit unidirectional bus used to send the addresses of memory registers and I/O devices.
Address Bus (A0–A15)
10
What is the maximum memory capacity the Z80 can address?
Up to 64 KB (65,536 Bytes).
11
It is an 8-bit bidirectional, tri-state bus that handles the transfer of data between the CPU, memory, and peripheral devices.
Data Bus (D0–D7)
12
It is an active low signal indicating that an op-code is currently being fetched from memory.
M1 (Machine Cycle One) signal
13
It indicates that the address bus currently holds a valid address for a memory read or write operation.
MREQ (Memory Request) signal
14
It indicates that the address bus currently holds a valid address for an Input/Output read or write operation.
IORQ (I/O Request) signal
15
They are general control signals indicating the direction of data (read or write operations).
RD (Read) and WR (Write) signals
16
A standard request from an external device needing CPU attention.
INT (Interrupt Request) signal
17
What makes the NMI (Non-Maskable Interrupt) different from a standard interrupt?
It is a high-priority interrupt request that the CPU cannot ignore.
18
What happens when the WAIT signal is low?
It forces the Z80 to add "wait states" (pauses) until slower memory or I/O devices are ready for data transfer.
19
It initializes and restarts the microprocessor.
RESET signal
20
It is used when an external device (like a DMA controller) wants to take control of the system buses.
BUSRQ (Bus Request) signal
21
It indicates that the CPU has acknowledged a BUSRQ and successfully released control of the buses.
BUSAK (Bus Acknowledge) signal
22
It is a maintenance signal used for refreshing Dynamic RAM (DRAM).
RFSH (Refresh) signal
23
It indicates the CPU has executed a HALT instruction and entered a resting state.
HALT signal
24
It uses an external single-phase clock source to synchronize all internal operations.
Clock (Phi) input
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